Hornet is a simple, fully open-source, FPGA-proven 32-bit RISC-V core.
- RV32IM instructions
- Machine mode support
- 5-stage pipelined microarchitecture
- Misaligned access support
- FPGA proven
In this repo, in addition to the core itself, you can also find supporting peripherals, software and SoC examples to help you get started.
We also provide a reference manual that explains how the core is designed and how it works, in detail; and a user guide that describes how you can use the core.
| Simplified Pipeline Diagram |
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Feel free to create an issue on GitHub or send an e-mail.