[CPU] I64 initial support.

include/oneapi/dnnl/dnnl.hpp

@@ -864,6 +864,8 @@ struct memory : public handle<dnnl_memory_t> {
         f64 = dnnl_f64,
         /// 32-bit signed integer.
         s32 = dnnl_s32,
+        /// 64-bit signed integer.
+        s64 = dnnl_s64,
         /// 8-bit signed integer.
         s8 = dnnl_s8,
         /// 8-bit unsigned integer.

include/oneapi/dnnl/dnnl_common_types.h

@@ -94,6 +94,8 @@ typedef enum {
     dnnl_boolean = 8,
     /// 1-bit integer.
     dnnl_bin = 9,
+    /// 64-bit signed integer.
+    dnnl_s64 = 10,
     /// Parameter to allow internal only data_types without undefined behavior.
     /// This parameter is chosen to be valid for so long as sizeof(int) >= 2.
     dnnl_data_type_max = 0x7fff,

src/common/c_types_map.hpp

@@ -160,6 +160,7 @@ const data_type_t bf16 = dnnl_bf16;
 const data_type_t f32 = dnnl_f32;
 const data_type_t f64 = dnnl_f64;
 const data_type_t s32 = dnnl_s32;
+const data_type_t s64 = dnnl_s64;
 const data_type_t s8 = dnnl_s8;
 const data_type_t u8 = dnnl_u8;
 const data_type_t boolean = dnnl_boolean;

src/common/dnnl_traits.hpp

@@ -63,6 +63,10 @@ struct prec_traits<data_type::s32> {
     typedef int32_t type;
 };
 template <>
+struct prec_traits<data_type::s64> {
+    typedef int64_t type;
+};
+template <>
 struct prec_traits<data_type::s8> {
     typedef int8_t type;
 };
@@ -96,6 +100,10 @@ struct data_traits<int32_t> {
     static constexpr data_type_t data_type = data_type::s32;
 };
 template <>
+struct data_traits<int64_t> {
+    static constexpr data_type_t data_type = data_type::s64;
+};
+template <>
 struct data_traits<int8_t> {
     static constexpr data_type_t data_type = data_type::s8;
 };

src/common/memory_zero_pad.cpp

@@ -285,7 +285,9 @@ static status_t zero_pad(const memory_t *memory, const exec_ctx_t &ctx) {
         case f16: return typed_zero_pad<f16>(memory, ctx);
         case bf16: return typed_zero_pad<bf16>(memory, ctx);
         case f32: return typed_zero_pad<f32>(memory, ctx);
+        case f64: return typed_zero_pad<f64>(memory, ctx);
         case s32: return typed_zero_pad<s32>(memory, ctx);
+        case s64: return typed_zero_pad<s64>(memory, ctx);
         case s8: return typed_zero_pad<s8>(memory, ctx);
         case u8: return typed_zero_pad<u8>(memory, ctx);
         case bin: return typed_zero_pad<u8>(memory, ctx);

src/common/type_helpers.hpp

@@ -89,6 +89,7 @@ inline size_t data_type_size(data_type_t data_type) {
         case f32: return sizeof(prec_traits<f32>::type);
         case f64: return sizeof(prec_traits<f64>::type);
         case s32: return sizeof(prec_traits<s32>::type);
+        case s64: return sizeof(prec_traits<s64>::type);
         case s8: return sizeof(prec_traits<s8>::type);
         case u8: return sizeof(prec_traits<u8>::type);
         case boolean: return sizeof(prec_traits<boolean>::type);
@@ -948,7 +949,7 @@ inline bool memory_desc_sanity_check(int ndims, const dims_t dims,
     if (ndims == 0) return true;
 
     bool ok = dims != nullptr && 0 < ndims && ndims <= DNNL_MAX_NDIMS
-            && utils::one_of(data_type, f16, bf16, f32, f64, s32, s8, u8, bin);
+            && utils::one_of(data_type, f16, bf16, f32, f64, s32, s64, s8, u8, bin);
     if (!ok) return false;
 
     bool has_runtime_dims = false;

src/cpu/reorder/cpu_reorder.cpp

@@ -34,6 +34,7 @@ regular_impl_list_map() {
             {{f32, bin, 0}, &regular_f32_bin_impl_list_map()},
             {{bf16, data_type::undef, 0}, &regular_bf16_impl_list_map()},
             {{f16, data_type::undef, 0}, &regular_f16_impl_list_map()},
+            {{s64, data_type::undef, 0}, &regular_s64_impl_list_map()},
             {{s32, data_type::undef, 0}, &regular_s32_impl_list_map()},
             {{s8, data_type::undef, 0}, &regular_s8_impl_list_map()},
             {{u8, data_type::undef, 0}, &regular_u8_impl_list_map()},

src/cpu/reorder/cpu_reorder.hpp

@@ -76,6 +76,7 @@ extern const impl_list_map_t &regular_f32_u8_impl_list_map();
 extern const impl_list_map_t &regular_f32_bin_impl_list_map();
 extern const impl_list_map_t &regular_bf16_impl_list_map();
 extern const impl_list_map_t &regular_f16_impl_list_map();
+extern const impl_list_map_t &regular_s64_impl_list_map();
 extern const impl_list_map_t &regular_s32_impl_list_map();
 extern const impl_list_map_t &regular_s8_impl_list_map();
 extern const impl_list_map_t &regular_u8_impl_list_map();

src/cpu/reorder/cpu_reorder_regular_s64.cpp

@@ -0,0 +1,61 @@
+/*******************************************************************************
+* Copyright 2020-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cpu/reorder/cpu_reorder.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+
+// clang-format off
+
+const impl_list_map_t &regular_s64_impl_list_map() {
+    static const impl_list_map_t the_map = REG_REORDER_P({
+        // s32 ->
+        {{s64, data_type::undef, 0}, {
+            REG_FAST_DIRECT_COPY(s64, f32)
+            REG_FAST_DIRECT_COPY(s64, s64)
+            REG_FAST_DIRECT_COPY(s64, s32)
+            REG_FAST_DIRECT_COPY(s64, s8)
+            REG_FAST_DIRECT_COPY(s64, u8)
+
+            DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64_jit_blk_reorder_t))
+            DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64_jit_uni_reorder_t))
+
+            DNNL_AARCH64_ONLY(CPU_REORDER_INSTANCE(aarch64_jit_uni_reorder_t))
+
+            DNNL_NON_X64_ONLY(REG_SR_BIDIR(s64, any, f32, nChw16c))
+            DNNL_NON_X64_ONLY(REG_SR_BIDIR(s64, any, s32, nChw16c))
+            DNNL_NON_X64_ONLY(REG_SR_BIDIR(s64, any, s8, nChw16c))
+            DNNL_NON_X64_ONLY(REG_SR_BIDIR(s64, any, u8, nChw16c))
+
+            REG_SR(s64, any, f32, any, fmt_order_any, spec_reference)
+            REG_SR(s64, any, s64, any, fmt_order_any, spec_reference)
+            REG_SR(s64, any, s32, any, fmt_order_any, spec_reference)
+            REG_SR(s64, any, s8, any, fmt_order_any, spec_reference)
+            REG_SR(s64, any, u8, any, fmt_order_any, spec_reference)
+
+            nullptr,
+        }},
+    });
+    return the_map;
+}
+
+// clang-format on
+
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl