Optimize graphics

alanjian85 · Nov 13, 2023 · 4ed174f · 4ed174f
1 parent dc20c96
commit 4ed174f
Show file tree

Hide file tree

Showing 2 changed files with 17 additions and 15 deletions.
diff --git a/src/main/scala/graphics/DiffInfo.scala b/src/main/scala/graphics/DiffInfo.scala
@@ -104,9 +104,9 @@ object DiffInfo {
 }
 
 class DiffInfo extends Bundle {
-  val e0 = SInt(32.W)
-  val e1 = SInt(32.W)
-  val e2 = SInt(32.W)
+  val e0 = SInt(24.W)
+  val e1 = SInt(24.W)
+  val e2 = SInt(24.W)
 
   val dj0 = SInt()
   val dj1 = SInt()
@@ -126,13 +126,13 @@ class DiffInfo extends Bundle {
 
   val a = SInt()
 
-  val r = SInt(32.W)
-  val g = SInt(32.W)
-  val b = SInt(32.W)
+  val r = SInt(24.W)
+  val g = SInt(24.W)
+  val b = SInt(24.W)
 
-  val er = SInt(32.W)
-  val eg = SInt(32.W)
-  val eb = SInt(32.W)
+  val er = SInt(24.W)
+  val eg = SInt(24.W)
+  val eb = SInt(24.W)
 
   val dquorj = SInt()
   val dquogj = SInt()

diff --git a/src/main/scala/graphics/Graphics.scala b/src/main/scala/graphics/Graphics.scala
@@ -6,15 +6,17 @@ import chisel3.util._
 
 class Graphics extends Module {
   def incrDiv(dquo: SInt, drem: SInt, divisor: SInt, quo: SInt, rem: SInt) = {
-    val rquo = WireDefault(quo + dquo)
-    val rrem = WireDefault(rem + drem)
+    val nquo = quo + dquo;
+    val nrem = rem + drem;
+    val rquo = WireDefault(nquo)
+    val rrem = WireDefault(nrem)
     when (drem > 0.S && rem >= divisor - drem) {
-      rquo := quo + dquo + 1.S
-      rrem := rem - divisor + drem
+      rquo := nquo + 1.S
+      rrem := nrem - divisor
     }
     when (drem < 0.S && rem <= -divisor - drem) {
-      rquo := quo + dquo - 1.S
-      rrem := rem + divisor + drem
+      rquo := nquo - 1.S
+      rrem := nrem + divisor
     }
     (rquo, rrem)
   }