Pinned Loading

1. RISCV32I_Core RISCV32I_Core Public

   The following repository contains the uArchitecture implemented for RISC-V ISA

   Verilog

2. Designing-Systolic-Array Designing-Systolic-Array Public

   The following repository houses a detailed implementation of the systolic array using Verilog and System Verilog

   SystemVerilog 4 1

3. SysVerilog_Cadence SysVerilog_Cadence Public

   This code repository contains the code used for the SystemVerilog Certification Labs

   SystemVerilog

4. Modified_AES256 Modified_AES256 Public

   A different approach than just using Rinjdahl's sbox values using Verilog.

   Verilog

5. ShortestPath_OptimizationSAT ShortestPath_OptimizationSAT Public

   Finding Minimum Distance to reach Two points in a Street Network and Placing Minimum Traffic Signals Across a Street Network using Vertex Cover Optimization

   C++

6. Obstacle-Avoidance-Wheelchair Obstacle-Avoidance-Wheelchair Public

   The following repository contains the details of our 3rd Year UG Major Project

   C